Universal shift register :
In the parallel load mode, the unit functions as a set of four D flip-flops. The two mode control bits, S1 and S0, provide four modes of operation:
(S1, S0) = 0 0: Retain the present state (do nothing).
0 1: Shift Right ( in the direction QA toward QD).
1 0: Shift Left (in the direction QD toward QA).
1 1: Parallel (Broadside) Load of A, B, C, D into QA, QB, QC, QD.
The shift and load operations occur synchronously on the rising edge of the single clock input which is connected internally to all four flip-flops.
Truth table for universal shift register
|
R_CLR |
Mode S1 S0 |
C4 CLK |
Serial in SL SR |
Parallel in A B C D |
Outputs
|
|
L |
X X |
X |
X X |
X X X X |
L L L L |
|
H |
X X |
¹  |
X X |
X X X X |
QA QB QC QD |
|
H |
H H |
 |
X X |
a b c d |
a b c d |
|
H |
L H |
 |
X H |
X X X X |
H QA QB QC |
|
H |
L H |
 |
X L |
X X X X |
L QA QB QC |
|
H |
H L |
 |
H X |
X X X X |
QB QC QD H |
|
H |
H L |
 |
L X |
X X X X |
QB QC QD L |
|
H |
L L |
X |
X X |
X X X X |
QA QB QC QD |
library ieee;
use ieee.std_logic_1164.all;
entity uni_shift is
port (clock, clear, sl_in, sr_in : in bit;
mode : in bit_vector ( 1 downto 0 );
data : in bit_vector ( 3 downto 0 );
q : inout bit_vector (3 downto 0 ));
end uni_shift;
architecture behav of uni_shift is
begin
process (clock, clear)
begin -- Asynchronous, active-low Clear input:
if clear = '0' then
q <= "0000" ; -- Rising edge-triggered D flip-flops:
elsif clock'event and clock = '1' then
case mode is
when "00" => null; -- "Do Nothing" mode: retain current flip-flop outputs
when "01" => q <= (q srl 1) or (sr_in & "000") ; -- Shift Right Serial Input
when "10" => q <= (q sll 1) or ("000" & sl_in) ; -- Shift Left Serial Input
when "11" => q <= data ; -- Parallel (Broadside) Load
end case;
end if;
end process;
end behav;