The importance of full scan lies in high-fault coverage for structural defects. Full scan testing of scan circuits is carried out in two phases. The first phase tests the scan register by a shift test. The shift test is used in both single-clock and two-clock designs. On the other hand in second phase, stuck-at faults in the combinational logic are considered and a program is used to generate the test vectors. Further, combinational test vectors are converted into scan sequences and applied to the circuit. The expected output response at primary outputs is specified at clock. Figure below shows full scan testing.
Advantages of full scan :
Disadvantages of full scan :