VHDL Introduction

VHDL Adavanced VHDL Arithmetic-Circuits

VHDL Concurrent-Statements

Attributes :

Data Attributes :

The pre-defined, synthesizable data attributes in VHDL are,

Signal Attributes :

Although the most signal attributes are used for simulation purposes only, the first two in the list bellow are synthesizable.

User-defined Attributes :

The attributes discussed in previous section are of the type HIGH, RANGE, EVENT, etc. and are called as pre-defined. However, VHDL also has the construction of user defined attributes. To have a user-defined attribute, it can declared and specified. The syntax is the follows,

Attribute declaration :

  ATTRIBUTE attribute_test: attribute_test;

Attribute specification :

ATTRIBUTE attribute_test OF target_test: class IS value;
where :
	attribute_test any data type (BIT, INTEGER, STD_LOGIC_VECTOR)
	value: ‘0’, 27, “00 11 10 01” 

Additonal Information