The pre-defined, synthesizable data
attributes in VHDL are,
dataâ€™LENGTH : Returns vector size.
dataâ€™RANGE : Returns vector range.
dataâ€™REVERSE_RANGE : Returns vector range in reverse order.
dataâ€™LOW : Returns lower array index.
dataâ€™HIGH : Returns upper array index.
dataâ€™LEFT : Returns leftmost array index.
dataâ€™RIGHT : Returns rightmost array index.
Signal Attributes :
Although the most signal attributes are used for simulation purposes only, the
first two in the list bellow are synthesizable.
tickâ€™EVENT : Returns true when an event occurs.
tickâ€™STABLE : Returns true if no event has occurred.
tickâ€™LAST_ACTIVE : Returns the time elapsed.
tickâ€™LAST_VALUE : Returns the value before the last event.
tickâ€™ACTIVE : Returns true.
tickâ€™LAST_EVENT : Returns the time elapsed since last event.
User-defined Attributes :
The attributes discussed in previous section are of the type HIGH, RANGE, EVENT, etc. and are called as pre-defined. However, VHDL also has the construction of user defined attributes. To have a user-defined attribute, it can declared and specified.
The syntax is the follows,
Attribute declaration :
ATTRIBUTE attribute_test: attribute_test;
Attribute specification :
ATTRIBUTE attribute_test OF target_test: class IS value;
attribute_test any data type (BIT, INTEGER, STD_LOGIC_VECTOR)
class : TYPE, SIGNAL, FUNCTION
value: â€˜0â€™, 27, â€œ00 11 10 01â€
This is an initiatory website for a simplified information about basics of electronics for beginners and advanced professionals..