Identical equality comparators are shown coded in three different ways. The single bit output is logic 1 when the two 6-bit input busses are the same; otherwise it is at logic 0. Fig. 6.7.1 : Simple equality comparator
library IEEE; use IEEE.STD_Logic_1164.all; use IEEE.Numeric_STD.all; entity equ_comp is port(A1,B1,A2,B2,A3,B3: in unsigned(5 downto 0); Y1,Y2,Y3: out std_logic); end equ_comp; architecture arch of equ_comp is begin process (A1, B1, A2, B2, A3, B3) begin Y1 <= '1'; for N in 0 to 5 loop if (A1(N) /=B1(N)) then Y1 <= '0'; exit; else null; end If; end loop; Y2 <= '0'; If (A2=B2) then Y2 <= '1'; end if; if(A3 = B3) then Y3<= '1'; else Y3 <= '0'; end if; end process; end arch;In the above code Extra parentheses enclosing "C /= D or E >= F" means that either one of these conditions and "A = B" must be true for the output to be at logic 1.