Combinational Logic Testing :
For testing the combinational logic circuitry a set of test patterns is generate which detect all possible fault conditions. The first approach to testing an n input circuit is to generate all the possible 2N input signal combinations by means of say an N bit counter (controllability) and observe the outputs for checking (observability). This is called exhaustive testing and is very effective, but is only practicable where N is relatively small. Many of patterns generated during exhaustive testing may not occur during the application of the circuit. Thus, it is productive to the possible faults and then generate a set of appropriate test vectors. The basic idea is to select a path from the site of the possible fault, through a sequence of gates leading to an output of the logic circuitry under test. Figure below shows the Combinational Logic Testing block schematic.