Design validation shows the structure and per¬formance of the subsystems. In this the floorplan is checked and the chip after assembly is checked. The block is then extracted, simulated and checked by using timing verifier. By checking the blocks the layout saves size, shape, and pinout of the block. Along with this, wiring errors, chip-level bugs and interface errors emitts an active-low signal and the receiving block an active-high signal. The design-rule checking requires CAD tools to build the integrated circuit and to find out the layout errors after tape out of the IC. The layouts designed using the editing systems provide design-rule checking.
Fig_Interconnect Routing Techniques