The mixed style modeling is any combination of behavior, data flow, and structural modeling in a single architecture body. In mixed style of modeling we could use component instantiation statements, concurrent signal assignment statements, sequential signal assignment statement. The most popular method to modeling large system is mixed style containing structural plus behavioral. For example if you want to write code for any microprocessor. First make the code for each block (register, ALU, control etc.) in behavioral format and then join them by structural method. Let take the one example shown in figure below. First divide it in parts as shown in the figure. We divide them in two part one is structural and other is dataflow.
library ieee; use ieee.std_logic_1164.all; entity example is port (A,B,C,D,E : in std_logic; Y : out std_logic); end example; architecture mixed of example is component nand2 is -- component declaration port (p1,p2 : in std_logic; 0 : out std_logic); end component; component xor2 is port (x1,x2 : in std_logic; 0 : out std_logic); end component; signal s:std_logic_vector (0 to 3); -- signal s assigns internal connections begin N1 : nand2 port map (A,B,s0); -- component instantiation N2 : nand2 port map (s0,s1,s3); X1 : xor2 port map (C,D,s1); S2<=D and E; -- data flow statement Y<= s3 or s2; end mixed;
Example 1 : Decoder In this decoder example, two Inverter component instantiation statements define the circuit responsible for determining the value of the signal S. This signal is read by behavioral part i.e. the process statement P. In this process, the values computed by the AND operation are assigned to the led output port.
architecture Mixed of Decoder is signal S: Bit_Vector(0 to 2); component Inverter port(A: in Bit; B: out Bit); end component; begin Inv1 : Inverter port map (A=>bcd(0), B=>S(0)); Inv2 : Inverter port map (A=>bcd(1), B=>S(1)); P : process (S, bcd) begin led(0) <= S(0) and S(1) after 5 ns; led(1) <= S(0) and bcd(1) after 5 ns; led(2) <= bcd(0) and S(1) after 5 ns; led(3) <= bcd(0) and bcd(1) after 5 ns; end process; end Mixed;