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VHDL has several types of pre-defined operators that are,

  • Shift operators
  • Arithmetic operators
  • Assignment operators
  • Logical operators
  • Relational operators
  • Concatenation operators

Shift operators :

  • Shift operators are used for shifting data.
  • The syntax is as follows,

<left operand>

<shift operation>

<right operand>.

  • The left should have type BIT_VECTOR, whereas the right operand should have INTEGER.
  • The shift operators are :

sll Shift left logic

srl Shift right logic

Arithmetic operators :

In arithmetic operators the data is of type INTEGER,SIGNED, UNSIGNED, or REAL. Further, if the std_logic_signed or the std_logic_unsigned package of the ieee library required to be used.

The arithmetic operators are :

  • + Addition
  • - Subtraction
  • * Multiplication
  • / Division
  • ** Exponentiation
  • MOD Modulus
  • REM Remainder
  • ABS Absolute value

Assignment operators :

The assignment operators are used to assign values to signals, variables, and constants. The assignment operators are,

<= Used to assign a value to a SIGNAL.

:= Used to assign a value to a VARIABLE, CONSTANT, or GENERIC.

=> Used to assign values to OTHERS.

Logical operators :

The logical operators are used to perform logical operations. The data should of type type BIT, STD_LOGIC, or STD_ULOGIC.

The logical operators are,

  • NOT
  • AND
  • OR
  • NAND
  • NOR
  • XOR
  • XNOR

Comparison operators :

Comparison operators are used for making comparisons. The data can be of any type. The comparison operators are,

  • = Equal to
  • /= Not equal to
  • < Less than
  • > Greater than
  • <= Less than or equal to
  • >= Greater than or equal to