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Layout Design Rules :

The layout design rules provide a set of guidelines for constructing the various masks needed in the fabrication of integrated circuits. Design rules are consisting of the minimum width and minimum spacing requirements between objects on the different layers.

The most important parameter used in design rules is the minimum line width. This parameter indicates the mask dimensions of the semiconductor material layers. Layout design rules are used to translate a circuit concept into an actual geometry in silicon.

The design rules is the media between circuit engineer and the IC fabrication engineer. The Circuit designers requires smaller designs with high performance and high circuit density whereas the IC fabrication engineer requires high yield process.

Minimum line width (MLW) is the minimum MASK dimension that can be safely transferred to the semiconductor material. For the minimum dimension design rules differ from company to company and from process to process.

To address this issue scalable design rule approach is used. In this approach rules are defined as a function of single parameter called ''. For an IC process '' is set to a value and the design dimensions are converted in the form of numbers. Typically a minimum line width of a process is set to 2 e.g. for a 0.25 m process technology '' equals 0.125 m.

Layered Representation of Layout :

The layer representation of layout converts the masks used in CMOS into a simple layout levels that are easier to visualise by the designers. The CMOS design layouts are based on following components :
(1) Substrates or Wells : These wells are p type for NMOS devices and n type for PMOS devices.
(2) Diffusion regions : At these regions the transistors are formed and also called as active layer. These are defined by n+ for NMOS and p+ for PMOS transistors.
(3) Polysilicon layers : These are used to form the gate electrodes of the transistors.
(4) Metal interconnects layers : These are used to form the power supply and ground rails as well as input and output rails.
(5) Contact and Via layers : These are used to form the inter layer connections.