Project Title: Flip -Flops for High Performance VLSI Applications
This project enumerates power that is low speed that is high of SET, DET, TSPC and C2CMOS Flip-Flop. As these flop that is flip have actually area that is little low power use, they can be employed in different applications like electronic VLSI clocking system, buffers, registers, microprocessors etc. The Flip-Flops are analyzed at 90 nm technologies. All these designed Flip-Flops and Latches are in contrast to regards to its area, transistor count, power propagation and dissipation delay DSCH that is using and tools. As chip technology that is manufacturing unexpectedly in the threshold of major evaluation, which shrinks chip in proportions and performance is implemented in design degree which develops the energy that is reduced chip using current CMOS micron design tools. This task proposes power that is speed that is low of sandals in which TSPC and C2CMOS flip flop in contrast to current flip flop topologies in term of its area, transistor count, power dissipation, propagation wait, parasitic values using the simulation outcomes in microwind.
* Single Edge-Triggered Flip-Flop (SET)
* Double Edge-Triggered Flip-Flop (DET)
* True Single-Phase-Clock Flip-Flop (TSPC)
* Clocked CMOS Flip-Flop (C2CMOS)