Home > vlsi projects > Proj 47 Power Gating Implementation with Body Tied Triple Well Structure

Project Title: Power Gating Implementation with Body-Tied Triple-Well Structure

Brief Introduction:

This project investigates power gating implementations that mitigate power noise. We focus on the human body connection of power-gated circuits, and examine the quantity of energy sound induced by power-on rush current additionally the share regarding the circuit that is power-gated a decoupling capacitance through the rest mode. To obtain the execution out that is best, created and fabricated a test chip in 65nm procedure. Experimental Results with measurement and simulation reveal that The circuit that is power-gated structure that is body-tied triple-well is The execution that is way better through the following three points; energy supply noise due to rush present, the share of decoupling capacitance throughout the sleep mode along with the leakage reduction As a total result of energy gating. With strong requirements for low energy VLSIs including portable devices to processors which are high-end energy gating method has become associated with the training that is relieving leakage that is common current of inactive circuits, and is intensively investigated for Reducing time that is wake-up leakage decrease that is making the most of. On an added hand, smaller wake-up time from remainder (power-gated) mode necessarily causes bigger rush present to gate that is recharge and PN-junction capacitances in the circuit that is which that is power-gated Results in a voltage that is big within the charged power supply system. To mitigate the fall induced by the rush present, a wake-up that is sensible procedure and an gating that is electric that is sophisticated are presented. Energy gating involves another function that is unwelcome intrinsic decoupling capacitances in the circuit that is power-gated Isolated from the charged power distribution community and their share as a decoupling capacitance cannot be expected. Consequently, the charged power sound in neighboring active circuits increases. Besides, the decoupling capacitance that is intrinsic Comprises of gate and PN-junction capacitances, as well as the PN-junction capacitance depends upon the framework that is okay. In, power noises in twin-well and structures which are triple-well Calculated and contrasted. Set alongside the twin-well structure, the floor bounce to the triple-well structure is larger due to the lack of the device that is p-substrate is resistive as well as the energy voltage fall is smaller due to the increase in the PN-junction capacitance.

Hardware Details:

  • PMOSs
  • NMOSs

Software Details:

  • 65nm CMOS process

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