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Rules for Designing Complementary CMOS Gates :

(1) NMOS devices connected in series correspond to an 'AND' function and the logic level at one end of the chain is transferred to the other end when all the gate inputs are high as shown in

Figure.

(2) NMOS devices connected in parallel correspond to an 'OR' function and the logic level at one end of the chain is transferred to the other end if atleast one of the inputs is high as shown in

Figure

(3) A series connection of PMOS conducts if both inputs are low represents the NOR function i.e. â€“â€“A ïƒ— â€“â€“B = â€“â€“â€“â€“â€“â€“A + B as shown in Figure.

(4) A parallel connection of PMOS conducts if any one of the inputs are low represents the NAND function. i.e. â€“â€“A + â€“â€“B = â€“â€“â€“â€“Â¬Â¬Â¬-AB as shown in Figure.

(5) Using De Morgan's theorems : (i) â€“â€“A + â€“â€“B = â€“â€“A ïƒ— â€“â€“B (ii) â€“â€“â€“â€“â€“â€“A ïƒ— B = â€“â€“A + â€“â€“B it is proved that PUN and PDN are of complementary CMOS gates are dual networks. i.e. A parallel connection of transistors in PUN corresponds to a series connection of transistors in PDN and vice-versa.

(6) In order to construct CMOS gates implement pull down network using series and parallel combination of NMOS transistors as per logic and derive pull up network by replacing series combination of NMOS by parallel combination of PMOS and also by replacing parallel combination of NMOS by series combination of PMOS transistors.

(7) Construct CMOS gate by combining the PDN and PUN.

(8) The complementary CMOS is inverting logic so implements only functions such as NAND, NOR and XNOR. In order to realize non-inverting Boolean function such as AND, OR and XOR an additional inverter stage is required at the output.

(9) The number of transistors required to implement an N input logic gate is 2N.