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    Home >> vlsi-projects >> Proj-62-Overlap-based-Logic-cell

    Project Title: Overlap based Logic cell

    Brief Introduction:

    Crosstalk and Clock routing is the problems that are major circuits which can be dynamic. Digital circuits are made to enhance design metrics like dependability, energy use, performance, and area. These approaches might be divided directly into fixed and logic that is powerful. Dynamic circuits are superior with regards to price and area compared To circuits being fixed. The CMOS that is main-stream logic static or powerful and pass transistor logic (PTL) designs are two architectures being major in applying the logic circuits. The PTL home has been explored in the form of Transmission Gates (TGs), Complementary PTL (CPL), Double PTL (DPL), and Gate Diffusion Input (GDI) logic styles. In a few logic functions like multiplexers, the TG logic is better set alongside the static CMOS architectures. However, the TG circuits become acutely sluggish in a group The Gate Diffusion Input (GDI) method, which is really a kind or sort of pass transistor logic (PTL) circuit, uses cells which can be two-transistor implement a logic function with just complexity that is minimal. The voltage move associated with the nodes being interior typically minimum which decreases the capability consumption that is powerful.

    Hardware Details:

    • CMOS technology

    Software Details:

    • Cadence tool
    • 180nm GPDK technology

    For more details