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Project Title: Power Efficient Logic Circuit Design

Brief Introduction:

The power dissipation in traditional CMOS circuits can be minimized through adiabatic strategy. By adiabatic strategy dissipation in PMOS system could possibly be minimized plus some of power Conserved at load capacitance is recycled in to the place that is accepted of as heat. Nevertheless the strategy that is adiabatic exceptionally influenced by parameter variation. The energy by making use of MICROWIND simulations usage is analyzed by variation of parameter. In analysis, two logic families, ECRL (Effective Charge recovery Logic) and PFAL (Positive Feedback logic that is adiabatic have been in comparison to main-stream CMOS logic for inverter NAND and NOR circuits. It's discovering that adiabatic strategy is response that is energy that is good is low application in a regularity range that is few.

Hardware Details:

  • NAND circuit
  • NOR circuits

Software Details:


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