1) 8-bit shift-left register with positive-edge clock, serial In, and serial out :
Serial-in, serial-out shift registers delay data by one clock time for each stage. They will store a bit of data for each register. A serial-in, serial-out shift register may be one to 64 bits in length, longer if registers or packages are cascaded.
library ieee;
use ieee.std_logic_1164.all;
entity shift_siso is
port (Clock, Sin : in std_logic;
Sout : out std_logic);
end shift_siso;
architecture behav of shift_siso is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
for i in 0 to 6 loop
temp(i+1) <= temp(i);
end loop;
temp(0) <= Sin;
end if ;
end process;
Sout <= temp(7);
end behav;
2) 8-bit shift-left register with positive-edge clock, asynchronous clear,
serial
in, and serial out :
library ieee;
use ieee.std_logic_1164.all;
entity shift_siso is
port (Clock, Sin, Clear : in std_logic;
Sout : out std_logic);
end shift_siso;
architecture behav of shift_siso is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock, Clear)
begin
if (Clear='1') then
temp <= (others => '0');
elsif (Clock'event and Clock='1') then
temp <= temp(6 downto 0) & Sin;
end if ;
end process;
Sout <= temp(7);
end behav;
3) 8-bit shift-left register with positive-edge clock, synchronous set,
serial In,
and serial out :
library ieee;
use ieee.std_logic_1164.all;
entity shift_SS is
port (Clock, Sin, Set : in std_logic;
Sout : out std_logic);
end shift_SS;
architecture behav of shift_SS is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock, Set)
begin
if (Clock'event and Clock='1') then
if (Set='1') then
temp <= (others => '1');
else
temp <= temp(6 downto 0) & Sin;
end if ;
end if ;
end process;
Sout <= temp(7);
end behav;
4) 8-bit shift-left register with positive-edge clock, serial in, and parallel out :
library ieee;
use ieee.std_logic_1164.all;
entity shift_sipo is
port (Clock, Sin : in std_logic;
Pout : out std_logic_vector(7 downto 0));
end shift_sipo;
architecture exam of shift_sipo is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
temp <= temp(6 downto 0)& Sin;
end if ;
end process;
Pout <= temp;
end exam;
5) 8-bit shift-left register with positive-edge clock, serial In, and serial out :
Serial-in, serial-out shift registers delay data by one clock time for each stage. They will store a bit of data for each register. A serial-in, serial-out shift register may be one to 64 bits in length, longer if registers or packages are cascaded.
library ieee;
use ieee.std_logic_1164.all;
entity shift_siso is
port (Clock, Sin : in std_logic;
Sout : out std_logic);
end shift_siso;
architecture behav of shift_siso is
signal temp: std_logic_vector(7 downto 0);
begin
process (Clock)
begin
if (Clock'event and Clock='1') then
for i in 0 to 6 loop
temp(i+1) <= temp(i);
end loop;
temp(0) <= Sin;
end if ;
end process;
Sout <= temp(7);
end behav;
6) 8 bit shift register using structural modeling:
library
IEEE;
use
IEEE.STD_LOGIC_1164.all;
entity
shift_8 is
port(
din : in STD_LOGIC;
clk : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end
shift_8;
architecture
structure of shift_8 is
component
d_ff is
port
(
clk : in STD_LOGIC;
din : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end component
;
signal
s : std_logic_vector(2 downto 0);
begin
u0 : d_ff port map (clk => clk, din => din,
reset => reset, dout => s(0));
u1 : d_ff port map (clk => clk, din => s(0),
reset => reset, dout => s(1));
u2 : d_ff port map (clk => clk, din => s(1),
reset => reset, dout => s(2));
u3 : d_ff port map (clk => clk, din => s(2),
reset => reset, dout => dout);
end
structure;
D Flip-Flop Design
library
IEEE;
use
IEEE.STD_LOGIC_1164.all;
entity
d_ff is
port(
clk : in STD_LOGIC;
din : in STD_LOGIC;
reset : in STD_LOGIC;
dout : out STD_LOGIC
);
end
d_ff;
architecture
behave of d_ff is
begin
process
(din,clk,reset) is
begin
if
(reset='1') then
dout <= '0';
elsif
(rising_edge (clk)) then
dout <= din;
end if
;
end process
;
end
behave;