We can design an n-bit binary up-down counter just like the up counter except that we need both an adder and a subtractor for the data input to the register. The VHDL code for the up-down counter, shown in follwing, is similar to the up counter code, but with the additional logic for the Down signal. If Down is asserted, then value is decremented by 1, otherwise it is incremented by 1. To make the code a little bit different, the counter output signal Q is declared as an integer that ranges from 0 to 16.
library ieee;
use ieee.std_logic_1164.all;
entity udcounter is
port (clock: in std_logic;
clear: in std_logic;
count: in std_logic;
down: in std_logic;
q: out integer range 0 to 15);
end udcounter;
architecture behav of udcounter is
begin
process (clock, clear)
variable value: integer range 0 to 15;
begin
if clear = '1' then
value := 0;
elsif (clock'event and clock='1') then
if count = '1' then
if down = '0' then
value := value + 1;
else
value := value - 1;
end if;
end if;
end if;
q <= value;
end process;
end behav;