Generics are mainly similar to constants whose values supplied externally. Similar to ports, generics are declared in entities and component declarations. The important advantage of generic is it provide a data transfer. The values of generics declared in an entity. The Syntax is :
generic ( generic_interface_list ) ;
library ieee ;
use ieee.std_logic_1164.all;
package components is
component system
generic ( n : integer := 4 ) ;
port ( cin: in std_logic ;
x, y: in std_logic_vector(n-1 downto 0) ;
s: out std_logic_vector(n-1 downto 0) ;
cout: out std_logic ) ;
end component ;
component SR
generic ( n : integer := 4 ) ;
port ( d: in std_logic_vector(n-1 downto 0) ;
resetn: in std_logic ;
e, clock: in std_logic ;
q: out std_logic_vector(n-1 downto 0) ) ;
end component;