VHDL has several types of pre-defined operators that are,
Shift operators :
sll Shift left logic
srl Shift right logic
Arithmetic operators :
In arithmetic operators the data is of type INTEGER,SIGNED, UNSIGNED, or REAL. Further, if the std_logic_signed or the std_logic_unsigned package of the ieee library required to be used.
The arithmetic operators are :
Assignment operators :
The assignment operators are used to assign values to signals, variables, and constants. The assignment operators are,
<= Used to assign a value to a SIGNAL.
:= Used to assign a value to a VARIABLE, CONSTANT, or GENERIC.
=> Used to assign values to OTHERS.
Logical operators :
The logical operators are used to perform logical operations. The data should of type type BIT, STD_LOGIC, or STD_ULOGIC.
The logical operators are,
Comparison operators :
Comparison operators are used for making comparisons. The data can be of any type. The comparison operators are,
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