Package : The part of VHDL code which is required repetitively is written in the form of COMPONENTS, FUNCTIONS, or PROCEDURES. This type of codes are then placed inside a PACKAGE and compiled in the LIBRARY. The syntax of PACKAGE is presented below.
PACKAGE package_name IS
	       (declarations)
	  END package_name;
	  [PACKAGE BODY package_name IS
	       (FUNCTION and PROCEDURE descriptions)
	  END package_name;]

As can be seen, the syntax is composed of two parts: PACKAGE and PACKAGE BODY. The first part is mandatory and contains all declarations, while the second part is necessary only when one or more subprograms (FUNCTION or PROCEDURE) are declared in the upper part, in which case it must contain the descriptions (bodies) of the subprograms.

PACKAGE and PACKAGE BODY must have the same name. The declarations list can contain the following: COMPONENT, FUNCTION, PROCEDURE, TYPE, CONSTANT, etc.

The example below shows a PACKAGE called my_package. It contains only TYPE and CONSTANT declarations, so a PACKAGE BODY is not necessary.

------------------------------------------------
	LIBRARY ieee;
	USE ieee.std_logic_1164.all;
 	------------------------------------------------
 	PACKAGE my_package IS
      		TYPE state IS (st1, st2, st3, st4);
    		TYPE color IS (red, green, blue);
      		CONSTANT vec: STD_LOGIC_VECTOR(7 DOWNTO 0) := "11111111";
 	END my_package;


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