In CMOS process several metal layers are used in interconnect wiring. Although 3 or 4 interconnect layers were sufficient for networks with a million or so FETs, the high-density compact systems are designed. On-chip wiring is important to the circuit designer to make a chip operational. Consider a wire shown in figure below which has width w, distance of d. The material layer with a height h. And Parasitic elements include resistance and capacitance.
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