Sequential Counter using D- Flipflop

For a D flip-flop design we must produce the logic function to drive DA, DB, and DC. We begin the design process by plotting the maps of below figure. The inputs to the IFL are the flip-flop outputs A, B, and C. These variables are used to plot the next state maps of fugure which are also the maps for DA, DB, and DC. This counter can be constructed as shown in figure.

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