CMOS NOR Gate : The truth table of the simple two input NOR gate is shown in Table. From the Table it is observed that the output function F is high only when all the inputs A and B are low.
Construction of PDN : The PDN of two input NOR gate is shown in Figure below. It consists of parallel combination of NMOS transistors that conduct when any one of the input is high and pulls the output F to logic low.
Construction of PUN :
The PUN of two input NOR gate is shown in
Figure below. Which is the dual network of the PDN and consists of series combination of two PMOS transistors. i.e. F is pulled to logic high when both the inputs A and B are low.
Construction of CMOS 2 input NOR gate :
The complete CMOS NOR gate is as shown in Figure below which is a combination of PUN and PDN networks shown in above Figure.
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