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Three input CMOS NAND gate

Construction of PDN :

The PDN of three input NAND gate is shown in Figure. It consists of series combination of three NMOS transistors that conducts when all the inputs are high and pulls the output ‘F’ to low level. Construction of PUN : The PUN is dual of PDN and it consists of parallel combination of three PMOS transistors as shown in Figure Construction of CMOS 3 input NAND gate : The complete CMOS NAND gate is shown in Figure below which is combination of PUN and PDN shown in above figures.

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