Project Title: Cache Memory Controller
This project is the design of efficient cache controller suited to found in FPGA-based processors.
Semiconductor memory which could run at rates comparable using the procedure about the processor exists; it is really not affordable to give you all of the memory that is main acutely rate semiconductor memory that is high. The issue could be eased by presenting a block that is tiny of price memory referred to as a cache between the memory that is primary the processor. Set-associative mapping compromise from a cache that is fully associative a main cache that is mapped as it increases speed. With regards to set cache that is associative we now have created cache controller. Spatial locality of guide is employed for tracking cache miss induced in cache memory. To be able to increase speed , less power usage And tabs on cache neglect in 4-way set cache that is associative, FPGA cache controller shall proposed in this project. The design work achieves less circuit complexity, less power use and high rate when it comes to resource use that is FPGA
* CACHE MEMORY
* CACHE CONTROLLER