Digital-CMOS-Design CMOS-Inverter CMOS-Layout-Design CMOS-Logic-Gates MOS-Capacitor MOSFET-Fundamentals Non-Ideal-Effects Pass-Transistor-Logic Propagation-Delay

AND gate

The truth table of AND gate is given as Table below.

From the truth table it is clear that the output F is high only when both the inputs A and B are high.

Construction of PDN :

The PDN of function F = A ? B is shown in Figure below which consists of series combination of two NMOS transistors.

Construction of PUN : The PUN of function F = A ? B is dual of the PDN which consists of parallel combination of two PMOS transistors as shown in Figure. Construction of CMOS AND gate : When we combine both the PDN and PUN the circuit will produce NAND gate i.e. –––––––A ? B in order to get the AND function F = A ? B extra inverter is connected at the output stage as shown in Figure below.

Additonal Information