Identifiers :

Identifiers are probably the most common operand. An identifier in VHDL is a user-defined name for any of this

(1) Constant,

(2) Variable,

(3) Function,

(4) Signal,

(5) Entity, port,

(6) Subprogram,

(7) Parameter,

and (8) Instantance

There are two types of identifiers : basic identifiers and extended identifiers.

Data Objects :

A data objects hold a value of specified type, which is created by means of an object declaration. In the following example signal is one of the type of data object. e.g. signal sl: std- logic

Type of data objects :

(i) Constant

(ii) File

(iii) Variable

(iv) Signals

1) Constant :

A constant is an object whose value may never be changed during the simulation process. The constant declaration contains one or more identifiers. The Syntax of constant is,

constant constant_name : type := value;

Example :

  constant width: integer:= 8;
  constant x: std_logic:= 16;
  constant delay: time:= 10ns;

2) File :

A sequence of value called file. The value can be read or write to file using read procedures and write procedures respectively. The Syntax of file is :

file identifier : subtype_indication [ file_open_information ];

Example :

  type IntegerFile is file of INTEGER;
  file F1: IntegerFile;

3) Variables :

A variable is an object with single current value. A signal value of given type having different values assigned to different times called as variable. The Syntax of variable is,:

variable variable_name : type;

variable variable_name : type := initial_value;

Example :

  variable A,B: bit;
  variable sum : std_logic_vector(7 downto 0);

4) Signal :

Signal is an object with a past history of values. The term signal refers to objects declared by signal declarations and port declarations. The Syntax of signal is :
signal signal_name : type;
signal signal_name : type := initial_value;

 Example 1 :

    signal A,B: std_logic;
    signal DELAY: time:=10ns;
  

 Example 2 :

  entity testing is
  port (A,B: in Std_Logic;
  C: out Std_logic);
  end entity VK;
  architecture Ex_testing of testing is
  signal Temp : Std_Logic;
  begin
  Temp<= A xor B;
  C<= not Temp;
  end architecture Ex_testing;

Each statement of the architecture Ex_testing may use any of the four signals: A, B, C declared as a port in the entity part (above the architecture section), Temp which is a single signal of the type Std_Logic



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