Digital-CMOS-Design CMOS-Inverter CMOS-Layout-Design CMOS-Logic-Gates MOS-Capacitor MOSFET-Fundamentals Non-Ideal-Effects Pass-Transistor-Logic Propagation-Delay

CMOS NAND Gate :

The truth table of the simple two input NAND gate is shown in Table .

From the Table, it is observed that the output function F is low only when all the inputs A and B are high. Construction of PDN :

The PDN of two input NAND gate is shown in

Figure below. It consists of series combination of NMOS transistors that conduct when both A and B are high and pulls the output ‘F’ to low.

Construction of PUN :

The PUN is the dual network of PDN and it consists of parallel combination of two PMOS transistors as shown in Figure below.

This means that F is pulled to logic high if A = 0 or

B = 0 which is equivalent to F = â€"â€"â€"â€"â€"â€"A  B.

Construction of CMOS 2 input NAND gate :

The complete CMOS NAND gate is as shown in Figure below, which is a combination of PUN and PDN.

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