Concurrent signal assignment is process for sequential assignment. The concurrent signal assignment statements are to be indicated into architecture. Concurrent signal assignment is independent of statements inside architecture and executed concurrently. For multiple assignments multiple drivers are created. Concurrent signal assignment types are, 1) Simple Concurrent Signal Assignments , 2) Conditional Concurrent Signal Assignment, 3) Selected Concurrent Signal Assignments and 4) Guarded Concurrent Signal Assignments Simple Signal Assignments : The syntax is : Name_of_signal <= expression;
Example 1 :
block signal A, B, Z: BIT; begin Z <= A and B; end block;
Example 2 :
entity simpsig is port (a, b, e: in std_logic; c, d: out std_logic); end simpsig; architecture xpld of simpsig is begin c <= a and b; -- creates an AND gate d <= e; -- connects two nodes end xpld;
Example 3 :
library ieee ; use ieee.std_logic_1164.all ; use ieee.std_logic_signed.all ; entity adder is port (Cin : in std_logic ; X, Y: in std_logic_vector (3 downto 0) ; S: out std_logic_vector (3 downto 0) ; Cout: out std_logic) ; end adder ; architecture behave_arch of adder is signal Sum: std_logic_vector (4 downto 0) ; begin Sum <= ('0' & X) + Y + Cin ; S <= Sum (3 downto 0); Cout <= Sum (4) ; end behave_arch ;
This is an initiatory website for a simplified information about basics of electronics for beginners and advanced professionals..