For...generate Statement :

For-generate statements can be nested, so it is possible to generate multi-dimensional arrays of component instances or other concurrent statements. The syntax is :

for identifier in range generate
			{ concurrent_statement }
	end generate;

Example : 4-bit full adder

entity full_add4 is
	port	(A,B : in std_logic_vector (3 downto 0);
		CIN : in std_logic;
		SUM : out std_logic_vector (3 downto 0);
		COUT  out std_logic);
	end full_add4;
	architecture arch of full_add4 is
	component fulladd is
	port	(FA,FB,FC : in std_logic;
		FSUM,FCOUT : out std_logic);
	end component;
	signal CAR: std_logic_vector (4 downto 0);
	begin
	CAR (0)<=CIN;
	VK: for k in 3 downto 0 generate
	FA: fulladd port map (CAR (k),A (k),B (k),CAR (k+1),sum (k));
	end generate VK;
	COUT<=CAR (4);
	end arch;


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