Digital-CMOS-Design CMOS-Inverter CMOS-Layout-Design CMOS-Logic-Gates MOS-Capacitor MOSFET-Fundamentals Non-Ideal-Effects Pass-Transistor-Logic Propagation-Delay

CMOS lambda Design Rules

CMOS ‘’ Design Rules :

The MOSIS stands for MOS Implementation Service is the IC fabrication service available to universities for layout, simulation, and test the completed designs. The MOSIS rules are scalable ‘’ rules.

The MOSIS design rules are as follows :

(1) Rules for N-well as shown in Figure below.
1. Minimum width = 10
2. Wells at same potential with spacing = 6
3. Wells at same potential = 0
4. Wells of different type, spacing = 8


(2) Rules for Active area shown in Figure below.
1. Minimum width = 3
2. Minimum spacing = 3
3. Source/Drain active to well
edge = 5
4. Substrate/well contact active
to well edge = 3


3) Rules for poly 1 as shown in Figure below.
1. Minimum width = 2
2. Minimum spacing = 2
3. Minimum gate extension of active = 2
4. Minimum field poly to active = 1


(4) Rules for contact to poly 1 as shown in Figure below.
1. Exact contact size = 2   2 
2. Minimum poly 1 overlap = 1 
3. Minimum contact spacing = 2 


(5) Rules for contact to active as shown in Figure below. 1. Exact contact size = 2  2 2. Minimum active overlap = 1 3. Minimum contact spacing = 2 4. Minimum spacing to gate of transistor = 2


(6) Rules for metal 1 as shown in Figure below.
1. Minimum width = 3
2. Minimum spacing = 3
3. Minimum overlap of poly contact = 1
4. Minimum overlap of active contact = 1


(7) Rules for via 1 as shown in Figure below.
1. Minimum size = 2  
2. Minimum spacing = 3
3. Minimum overlap by metal 1 = 1


(8) Rules for metal 2 as shown in Figure below.
1. Minimum size = 3
2. Minimum spacing = 4


(9) Rules for metal 3 as shown in Figure below.
1. Minimum width = 6
2. Minimum spacing = 4


FaceBook
Likes
Additonal Information