VHDL Introduction

VHDL Adavanced VHDL Arithmetic-Circuits

VHDL Concurrent-Statements

Configuration Specification :

The component instantiation indicates the entity part of the code. The association of entity and architecture is shown by the configuration specification. Component specification is mainly shown in the declarative part. Therefore, the components are configured in the architecture. The configuration specification is less hectic task of the code. The generic map and port map clauses are also used in configuration specification.

The Syntax is :

Example :

entity INV_ERTER is 
		generic (Propagation_delay : TIME := 5 ns); 
		port ( IN1 : in BIT; OUT1 : out BIT); 
          architecture STRUCT_Inv of INV_ERTER is 
		OUT1 <= not IN1 after PropTime; 
	end STRUCT_Inv; 
           entity TEST_ INV_ERTER is end TEST_ INV_ERTER; 
          architecture STRUCT_Test of TEST_ INV_ERTER is 
	signal S1, S2 : BIT := '1'; 
	component INV_CMP is 
		generic (TimeH : TIME); 
		port ( IN_A : in BIT; OUT_A : out BIT ); 
	end component; 
	for LH : INV_CMP 
		use entity INVERTER (STRUCT_Inv) 
		generic map (Propagation_delay => TimeH) 
		port map (IN1 => IN_A, OUT1 => OUT_A); 
	LH : INV_COMP generic map (10 ns) 
		port map (S1, S2); 
	end STRUCT_Test; 

Additonal Information