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Compound Gates :

The compound gates are formed by combining the series and parallel structures of transistors. Example below shows the construction of compound gates. Using complementary CMOS logic consider the implementation of complex CMOS gate whose function is F = â€"â€"â€"â€"â€"â€"â€"â€"â€"â€"â€"â€"A  (B + C).

The first step in the implementation of logic gate is to derive pull down network as shown in Figure below by using the fact that NMOS devices in series implements AND function and parallel NMOS transistors implements the OR function.

The next step is to use duality to derive PUN in hierarchical fashion as shown in

Figure below.

The complete logic function is then constructed by using the combination of both PUN and PDN as shown in Figure below

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