The pre-defined, synthesizable data attributes in VHDL are,
The attributes discussed in previous section are of the type HIGH, RANGE, EVENT, etc. and are called as pre-defined. However, VHDL also has the construction of user defined attributes. To have a user-defined attribute, it can declared and specified. The syntax is the follows,
ATTRIBUTE attribute_test: attribute_test;
Attribute specification :
ATTRIBUTE attribute_test OF target_test: class IS value;
where : attribute_test any data type (BIT, INTEGER, STD_LOGIC_VECTOR) class : TYPE, SIGNAL, FUNCTION value: â€˜0â€™, 27, â€œ00 11 10 01â€
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