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    Home >> vlsi-projects >> Proj-32-SMART-SENSOR

    Project Title: SMART SENSOR

    Brief Introduction:

    The project target VHDL model of smart sensor is proposed to obtain treatment for the challenge of developers. It's an platform that is optimal using algorithm for smart sensor product for noise decrease (sound termination of vocals signal) utilizing IEEE 1451 standard. There are many researches on sound termination but sensor that is using is smartsensing time that is genuine as a result of the interfered sound might be more effective. To reach good result the signal is first using that is sensed sensing procedure it is conditioned and processed using VHDL. The VHDL system developed will act whilst the sensor that is smart as above mentioned action. The VHDL allows the simulation that is complete of system and thus it is possible to simulate together parameter of various domain.

    Hardware Details:

    • smart sensor
    • FPGA kit

    Software Details:

    • VHDL
    • Xilinx 9.2 version

    Block Diagram:

    For more details

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