Digital-CMOS-Design CMOS-Inverter CMOS-Layout-Design CMOS-Logic-Gates MOS-Capacitor MOSFET-Fundamentals Non-Ideal-Effects Pass-Transistor-Logic Propagation-Delay

CMOS OR gate.

The truth table of ‘OR’ gate is shown in Table. From the truth table it is clear that the output F is low when both the inputs A and B are low and high when any one of the input is high.

Construction of PDN :

Construction of CMOS ‘OR’ gate :

When we combine both the PDN and PUN the circuit will produce NOR gate i.e.

F = ––––––A + B in order to get ‘OR’ gate OR function i.e. F = A + B extra inverter stage is connected at the output as shown in Figure below.

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