Conventional design modeling tools used by hardware engineer includes paper
and pencil, schematic capture programs and bread boarding facilities. The newest and
most promising change in this design modeling is the invention of Hardware Description Languages (HDLs). HDLs describes the hardware for the simulation, modeling, testing, design and documentation. These languages show the functional and wiring details of digital systems. Some HDLs consist of a simple set of symbol and notations that replace schematic diagrams of digital circuits, while others are more formally define and may present the hardware at one or more levels of abstraction. Available software for HDL includes simulators and hardware synthesis programs. A simulation program can be used for design verification, while a synthesis tools are used for automatic hardware generation. A test generation program depends upon a hardware description language for providing it with a netlist format, test application testbench and fault injection. HDL is any language from a class of computer languages for formal description of electronic circuits. The HDL explores the electronic circuit operations, designs, and tests. VHDL and Verilog are the popular Hardware Description Languages in academia and industries. HDLs are mainly used to describe the architecture and behaviour of the integrated circuits.
Advantages of HDL
1) You can verify design functionality early in the design written as an HDL description.
2) Design simulation at this higher level before implementation at gate level, allow you to test architectural and design decisions.
3) HDL compilers provide logic synthesis and optimization, so you can automatically convert a HDL description to a gate level implementation in given technology.
4) Reduced Non-recurring Engineering (NRE) costs.
5) Design reuse is enabled.
6) Increased flexibility to design changes.
7) Faster exploration of alternative architectures.
8) Better and easier design auditing and verification.
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