Digital-CMOS-Design CMOS-Inverter CMOS-Layout-Design CMOS-Logic-Gates MOS-Capacitor MOSFET-Fundamentals Non-Ideal-Effects Pass-Transistor-Logic Propagation-Delay

Static Power Consumption

The static power dissipation is due to the leakage currents. The static or steady state power dissipation of the circuit is given by,

Pstat = Ileakage · VDD

where Ileakage is the leakage current that flows between VDD and ground in the absence of switching activity. The leakage current of the CMOS inverter is equal to zero in ideal case, since the pMOS and nMOS devices never ON simultaneously in steady state operation. But the leakage current is flowing through the reverse biased diode junctions of the transistors located between sources or drain and substrate. This contribution of current is very small and can be neglected. Hence the contribution of static power dissipation component in CMOS inverter is very less and generally neglected.

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