Comparators :

A comparator compares two or more inputs using one, or a number of different comparisons. Comparators are implemented using if statement. Any two data objects are compared using equality and relational operators in the expression part of the if statement.

Table Equality, relational and logical operators

Comparator using Multiple Comparisons :
library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.numeric_std.all; 

entity mul_comp is
         port (A,B,C,D,E,F: in unsigned(2 downto 0);
                  Y: out std_logic);
end mul_comp;

architecture arch of mul_comp is 
begin
      process (A,B,C,D,E,F)
          begin
               if (A = B and (C /= D or E >= F )) then
                    Y <= '1'; 
               else
                   Y <= '0';
               end if;
       end process; 
end arch;
2 Bit Comparator using Unsigned Integer :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;     -- this use clause is necessary for unsigned integer 

entity cmp_int is
   port( A,B: in unsigned(1 downto 0);                  -- 2 bit unsigned input
         AequalB, AgreaterB, AlessB: out std_logic);
end cmp_int;

architecture cmp_arch of cmp_int is
begin
AequalB <= ‘1’ when A=B else ‘0’;
AgreaterB <= ‘1’ when A>B else ‘0’;
 AlessB <= ‘1’ when A< B else ‘0’;
end cmp_arch;
A) 1-bit comparator cell :
library IEEE;
use IEEE.std_logic_1164.all;

entity cmp_cell is
   port( a,b: in std_logic;
         Cin: in std_logic_vector(1 downto 0);
         Cout: out std_logic_vector(1 downto 0));
end cmp_cell;

architecture cmp_cell of cmp_cell is
begin
   process(Cin,a,b)
     begin
       if Cin=”10” then 
          Cout<=”10”;
       elsif Cin=”01” then 
          Cout<=”01”;
       elsif Cin=”00” and a=b then 
          Cout<=”00”;
       elsif Cin=”00” and a>b then 
          Cout<=”01”;
       elsif Cin=”00” and a
B)      8-bit
comparator using 1-bit comparator cell :
library IEEE;
use IEEE.std_logic_1164.all;

entity comparator_8 is
   port( A,B: in std_logic_vector(7 downto 0);
         CMPIN: in std_logic_vector(1 downto 0);
         CMPOUT: out std_logic_vector(1 downto 0));
end comparator_8;

architecture cmp_8 of comparator_8 is
component cmp_cell
     port( a,b: in std_logic;
           Cin: in std_logic_vector(1 downto 0);
           Cout: out std_logic_vector(1 downto 0));
end component;
signal OUT0,OUT1,OUT2,OUT3,OUT4,OUT5,OUT6:std_logic_vector(1 downto 0);

begin
cell0:cmp_cell port map (A(0),B(0),CMPIN,OUT0);
cell1:cmp_cell port map (A(1),B(1),OUT0,OUT1);
cell2:cmp_cell port map (A(2),B(2),OUT1,OUT2);
cell3:cmp_cell port map (A(3),B(3),OUT2,OUT3);
cell4:cmp_cell port map (A(4),B(4),OUT3,OUT4);
cell5:cmp_cell port map (A(5),B(5),OUT4,OUT5);
cell6:cmp_cell port map (A(6),B(6),OUT5,OUT6);
cell7:cmp_cell port map (A(7),B(7),OUT6,CMPOUT);
end cmp_8;



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Operators

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Equality and relational

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