Selected Signal

Assignments (with Select Statement) :

In Selected signal assignment all choices of expression included. The others clause last choice. Ranges and selections are used. Overlap should be rejected. not allowed for choices to overlap. The behavior is also called selected signal assignment.
The syntax is :
with choice_expression select
target
<= { expression when choices, }
expression
when choices;

Examples :

Example 1 :

signal A, B, C, D, Z: BIT;
 signal CONTROL: bit_vector(1 downto
0);
 .
. .
 with CONTROL select
 Z <= A
when 00;
 B when 01;
 C when 10;
 D when 11;
 Example 2 : 
Process
Equivalent to Selected Signal Assignment
 process(CONTROL, A, B, C, D)
 begin
 case CONTROL is
 when 0
=> Z <= A;
 when 1 =>
Z <= B;
 when 2 =>
Z <= C;
 when 3
=> Z <= D;
 end case;
 end process; 


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