Multiplier : 1) 8 bit Signed fixed point multiplier :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_signed.all;

entity multi is
	port(   A : in std_logic_vector(7 downto 0);
	           B : in std_logic_vector(7 downto 0);
	           Q : out std_logic_vector(15 downto 0));
end multi

architecture multi_arch of multi is
begin
	Q <= A * B;
end multi_arch;
2) 8 bit unsigned fixed point multiplier :
library IEEE;
use IEEE.std_logic_1164.all;
use IEEE.std_logic_unsigned.all;

entity multi is
	port (  A : in std_logic_vector(7 downto 0);
	           B : in std_logic_vector(7 downto 0);
	           Q : out std_logic_vector(15 downto 0));
end multi;

architecture multi_arch of multi is
begin
	Q <= A * B;
end multi_arch;



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