Digital-CMOS-Design CMOS-Inverter CMOS-Layout-Design CMOS-Logic-Gates MOS-Capacitor MOSFET-Fundamentals Non-Ideal-Effects Pass-Transistor-Logic Propagation-Delay

RC Delay Model of Inverter | MOSFET-Fundamentals

The RC delay model of an inverter is shown in Figure below which represents transistor as a resistance and a charging or discharging capacitance.

Digital circuits usually modeled as a first order RC networks as shown in Figure below

. When we apply a step input going from 0 to V the transient response of this circuit is an exponential function and is given by the expression.

Vout (t) = 1  e t V Where  = RC called as time constant.

The time to reach the 50% point is given as : t = ln (2)  = 0.69  = 0.69 RC.

Also, time to reach the 90% point is given as : t = ln (9)  = 2.2  = 2.2 RC.

To derive the equation for propagation delay the voltage dependence of the on resistance and the load capacitor is considered. The equivalent on resistance for charging or discharging paths is given as :

Req = 1VDD2 VDDVDD2 VIDSAT (1 + V)  dV

= 34 VDDIDSAT 1  79  VDD

Where, IDSAT = n Cox WL (VDD  VTH) VDSAT  VDSAT22

Now we can easily derive the expression for propagation delay

i.e. tpHL = ln (2) Reqn CL = 0.69 Reqn CL

Similarly

tpLH = ln (2) Reqp CL = 0.69 Reqp CL

where Reqn is the equivalent on resistance of NMOS and Reqp is the equivalent on resistance of PMOS transistor. The overall propagation delay of inverter is the average of these two values which is given as :

tp = tpHL + tpLH2 = 0.69 CL Reqn + Reqp2

Here we assumed that the equivalent load capacitance is identical to both the high to low and low to high transitions. i.e. CLHL = CLLH = CL.

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