The ICT PEEL Arrays are large PLAs which include logic macrocells with flip-flops and feedback to the logic planes. Figure below shows a programmable AND-plane that feeds a programmable OR-plane. The outputs of the OR-plane are divided into groups of four and each group gives input to any of the logic cells. The logic cells provide registers for the sum terms and can feed-back the sum terms to the AND-plane. Because of PLA-like structure, logic capacity of PEEL Arrays is somewhat difficult to measure compared to the CPLDs. PEEL Arrays offer relatively few I/O pins, with the largest part being offered in a 40 pin package. The logic cell in the PEEL Arrays consists of a flip-flop, configurable as D, T, or JK, and two multiplexers. The multiplexers produce output of the logic cell and provide a registered or combinational output. The logic cell outputs connect to an I/O pin.

Fig_ICT PEEL Arrays

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