VHDL Adavanced VHDL Arithmetic-Circuits

VHDL Concurrent-Statements

Counters

Flipflops

Logic-Circuits

Logic-Gates

Sequential-Statements

Shift-Registers

6.8.2 Binary to Gray Code Converter :

A Gray code is one in which adjacent numbers differ by one symbol. There are many Gray Codes, even in binary. They can be devised in any base. When Gray (or Gray code) is used without specifying which one, what is meant is reflected Binary Gray. To convert binary to Gray, it is only necessary to XOR the original unsigned binary with a copy of itself that has been right shifted one place. That is easy to do with common instructions.

1) Using selected signal assignment :

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY bin2grey IS

PORT (bin : IN std_logic_vector(3 DOWNTO 0);

grey : OUT std_logic_vector(3 DOWNTO 0));

END bin2grey;

ARCHITECTURE exam OF bin2grey IS

BEGIN

WITH bin SELECT

grey <= “0000” WHEN "0000”,

“0001” WHEN ”0001”,

“0011” WHEN ”0010”,

“0010” WHEN ”0011”,

“0110” WHEN ”0100”,

“0111” WHEN ”0101”,

“0101” WHEN ”0110”,

“0100” WHEN ”0111”,

“1100” WHEN ”1000”,

“1101” WHEN ”1001”,

“1111” WHEN ”1010”,

“1110” WHEN ”1011”,

“1010” WHEN ”1100”,

“1011” WHEN ”1101”,

“1001” WHEN ”1110”,

“1000” WHEN OTHERS;

END exam;

2) Using case statement :

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

ENTITY bin2grey IS

PORT (bin : IN std_logic_vector(3 DOWNTO 0);

grey : OUT std_logic_vector(3 DOWNTO 0));

END bin2grey;

ARCHITECTURE exam OF bin2grey IS

begin

process (bin)

begin

case bin is

when “0000” => grey <= "0000";

when “0001” => grey <= "0001";

when “0010” => grey <= "0011";

when “0011” => grey <= "0010";

when “0100” => grey <= "0110";

when “0101” => grey <= "0111";

when “0110” => grey <= "0101";

when “0111” => grey <= "0100";

when “1000” => grey <= "1100";

when “1001” => grey <= "1101";

when “1010” => grey <= "1111";

when “1011” => grey <= "1110";

when “1100” => grey <= "1010";

when “1101” => grey <= "1011";

when “1110” => grey <= "1001";

when “1111” => grey <= "1000";

end case;

end process ;

END exam;

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