VHDL Adavanced VHDL Arithmetic-Circuits

VHDL Concurrent-Statements

Counters

Flipflops

Logic-Circuits

Logic-Gates

Sequential-Statements

Shift-Registers

1) 4 Bit Ripple Up Counter :

library IEEE;

use IEEE.std_logic_1164.all;

entity counter is

port ( CLK : in std_logic; -- Clock input CLK active low

CLR : in std_logic; -- Asynchronous clear input CLR active high

SET : in std_logic; -- Asynchronous set input SET active high

OE : in std_logic; -- Output enable input OE active high

Q: out std_logic_vector(3 downto 0));

end counter;

architecture counter_arch of counter is

signal TEMP_Q : std_logic_vector(3 downto 0);

begin

BIT0 : process(CLK, CLR, SET)

begin

if CLR = '1' then

TEMP_Q(0) <= '0';

elsif SET = '1' then

TEMP_Q(0) <= '1';

elsif falling_edge(CLK) then

TEMP_Q(0) <= not TEMP_Q(0);

end if;

end process;

BIT1 : process(TEMP_Q(0), CLR, SET)

begin

if CLR = '1' then

TEMP_Q(1) <= '0';

elsif SET = '1' then

TEMP_Q(1) <= '1';

elsif falling_edge(TEMP_Q(0)) then

TEMP_Q(1) <= not TEMP_Q(1);

end if;

end process;

BIT2 : process(TEMP_Q(1), CLR, SET)

begin

if CLR = '1' then

TEMP_Q(2) <= '0';

elsif SET = '1' then

TEMP_Q(2) <= '1';

elsif falling_edge(TEMP_Q(1)) then

TEMP_Q(2) <= not TEMP_Q(2);

end if;

end process;

BIT3 : process(TEMP_Q(2), CLR, SET)

begin

if CLR = '1' then

TEMP_Q(3) <= '0';

elsif SET = '1' then

TEMP_Q(3) <= '1';

elsif falling_edge(TEMP_Q(2)) then

TEMP_Q(3) <= not TEMP_Q(3);

end if;

end process;

Q <= TEMP_Q when OE = '1' else ( others => 'Z');

end counter_arch;

2) 4-Bit Synchronous Counter :

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

entity cntrnbit is

generic (n : positive := 4); -- Using this statement counter can be programed for any no. of bits

port (clock, reset, enable : in std_logic;

count : out std_logic_vector((n-1) downto 0));

end cntrnbit;

architecture vk of cntrnbit is

signal count_int : std_logic_vector((n-1) downto 0);

begin

process

begin

wait until rising_edge(clock);

if reset = '1' then

count_int <= (others => '0');

elsif enable = '1' then

count_int <= count_int + 1;

else

null;

end if;

end process;

count <= count_int;

end vk;

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