VHDL Adavanced VHDL Arithmetic-Circuits

VHDL Concurrent-Statements

Counters

Flipflops

Logic-Circuits

Logic-Gates

Sequential-Statements

Shift-Registers

1) 8 Bit Synchronous Johnson Up Counter :

library IEEE;

use IEEE.std_logic_1164.all;

entity counter is

port ( CLK : in std_logic; -- Clock input CLK active high

CLR : in std_logic; -- Synchronous clear input CLR active high

SET : in std_logic; -- Synchronous set input SET active high

Q : out std_logic_vector(7 downto 0));

end counter;

architecture counter_arch of counter is

signal TEMP_Q : std_logic_vector(7 downto 0);

begin

process(CLK)

begin

if rising_edge(CLK) then

if CLR = '1' then

TEMP_Q <= (others => '0');

elsif SET = '1' then

TEMP_Q <= (others => '1');

else

TEMP_Q <= TEMP_Q(6 downto 0) & ( not TEMP_Q(7));

end if ;

end if;

end process;

Q <= TEMP_Q;

end counter_arch;

2) 8 Bit Asynchronous Johnson Up Counter :

library IEEE;

use IEEE.std_logic_1164.all;

entity counter is

port ( CLK : in std_logic; -- Clock input CLK active high

CLR : in std_logic -- Asynchronous clear input CLR active high

SET : in std_logic; -- Asynchronous set input SET active high

Q : out std_logic_vector(7 downto 0));

end counter;

architecture counter_arch of counter is

signal TEMP_Q : std_logic_vector(7 downto 0);

begin

process (CLK, CLR, SET)

begin

if CLR = '1' then

TEMP_Q <= (others => '0');

elsif SET = '1' then

TEMP_Q <= (others => '1');

elsif rising_edge(CLK) then

TEMP_Q <= TEMP_Q(6 downto 0) & ( not TEMP_Q(7));

end if;

end process;

Q <= TEMP_Q;

end counter_arch;

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