Example :
entity INV_ERTER is
generic (Propagation_delay : TIME := 5 ns);
port ( IN1 : in BIT; OUT1 : out BIT);
end INVERTER;
architecture STRUCT_Inv of INV_ERTER is
begin
OUT1 <= not IN1 after PropTime;
end STRUCT_Inv;
entity TEST_ INV_ERTER is end TEST_ INV_ERTER;
architecture STRUCT_Test of TEST_ INV_ERTER is
signal S1, S2 : BIT := '1';
component INV_CMP is
generic (TimeH : TIME);
port ( IN_A : in BIT; OUT_A : out BIT );
end component;
for LH : INV_CMP
use entity INVERTER (STRUCT_Inv)
generic map (Propagation_delay => TimeH)
port map (IN1 => IN_A, OUT1 => OUT_A);
begin
LH : INV_COMP generic map (10 ns)
port map (S1, S2);
end STRUCT_Test;