NAND stands for NOT AND. An AND gate followed by a NOT circuit makes it a NAND gate Figure shows the circuit symbol of a two-input NAND gate. The truth table of a NAND gate is obtained from the truth table of an AND gate by complementing the output entries. The output of a NAND gate is a logic ‘0’ when all its inputs are a logic ‘1’. For all other input combinations, the output is a logic ‘1’. NAND gate operation is logically expressed as Y = (AB)’
CMOS NAND Gate
The circuit below has two inputs and one output. Whenever at least one of the inputs is low, the corresponding P-type transistor will be conducting while the N-type transistor will be closed. Consequently, the output voltage will be high. Conversely, if both inputs are high, then both P-type transistors at the top will be open circuits and both N-type transistors will be conducting. Hence, the output voltage is low. The function of this gate can be summarized by the table. If logical 1’s are associated with high voltages then the function of this gate is called NAND for negated AND. Again, there is never a conducting path from the supply voltage to ground.