Advanced Micro Devices (AMD) CPLDs

Advanced Micro Devices manufactures a CPLD family with five sub-families called Mach 1 to Mach 5. The Mach device consists of multiple PAL blocks. All Mach chips are based on EEPROM. Figure below shows a Mach 4 chip, showing the multiple 34V16 PAL-like blocks, and the interconnect, called Central Switch Matrix, for connecting the blocks together. All connections in Mach 4 between one PAL block and another are routed through the Central Switch Matrix. The device viewed not only as a collection of PALs, but also as a single large device. Since all connections travel through the same path, timing delays of circuits implemented in Mach 4 are predictable. A Mach 4 PAL-like block has 16 outputs and a total of 34 inputs. However, there are two key differences between this block and a normal PAL are, 1)There is a product term allocator between the AND-plane and the macrocells and 2) There is an output switch matrix between the OR-gates and the I/O pins. The product term allocator distributes and shares product terms from the AND-plane to OR-gates require them. The output switch matrix makes it possible for any macrocell output to drive any of the I/O pins connected to the PAL block

Advanced Micro Devices (AMD) CPLDs

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